In a microprocessor, instructions are fetched for execution sequentially until a branch occurs. A branch causes a change in the address from which instructions are fetched and may be associated with delays in instruction fetch throughput. For example, branches may need to be evaluated to determine whether to take the branch as well as what the branch destination is. However, branches cannot be evaluated until the branch has actually entered the instruction execution pipeline. Branch delays are associated with the difference between the time that the branch is fetched and the time that the branch is evaluated to determine the outcome of that branch and thus what instructions need to be fetched next.
Branch prediction helps to mitigate this delay by predicting the existence and outcome of a branch instruction based upon instruction address and on branch evaluation history. Branch prediction techniques may use a global history of branch conditional decisions (e.g., taken or not-taken), and the current program counter value to make a prediction of whether a branch exists and whether that branch should be taken. A branch target buffer stores information that associates program counter addresses with branch targets. The existence of an entry in the branch target buffer implicitly indicates that a branch exists at the program counter associated with that entry. A branch predictor can use the global history and branch target buffer data to make branch prediction decisions. Because of the delays associated with branch instructions, efficient branch prediction and well-designed branch prediction logic is important in microprocessor design.